The present invention is related to phase-locked loops and, more particularly, to divider circuits suitable for high speed clock rates.
Frequency synthesis by a phase-locked loop (PLL) circuit is a very common technique in widespread use in many sorts of electronic equipment. For example, frequency synthesis is now also used in computers and PLLs allow a high frequency clock to be generated from a lower frequency reference clock. This function is generally integrated onto a CMOS integrated circuit and is called a clock generator or clock synthesizer. A major problem with these integrated circuits is the accuracy of the synthesized clock.
PLL circuits typically have a programmable divider or counter block in the feedback path from the voltage-controlled oscillator (VCO) which generates the output signal. The tuning range of the VCO is normally quite large to allow the VCO to operate at high frequencies. This makes it difficult for the feedback divider block to operate accurately and destroys the accuracy of the synthesized clock signal. One solution to this problem is the placement of a prescalar divider or counter circuit between the VCO and the divider block in the feedback path. However, the fine tuning of the clock signal is lost and the tuning resolution of the signal is coarsened.
The present invention solves or substantially mitigates this problem with a programmable PLL having fine tuning of an accurate and high-speed output signal.